The project was developed by the CIN Researcher Parampuneet Kaur Thind

Project Summary

• The collaboration with ESA Φ-lab led to the development of a framework that enables Neural Architecture Search (NAS) on hardware, a key advancement for optimizing deep learning models for onboard satellite deployment.
• Traditional optimization and compression techniques (e.g., pruning, quantization) are typically applied post hoc to a trained model, often leading to a significant drop in accuracy. NAS, however, integrates hardware constraints into the model design from the start, ensuring optimal trade-offs between accuracy and efficiency.
• The framework supports various model compression techniques, including quantization, pruning, knowledge distillation, and tensor decomposition, to optimize storage, power consumption, and computational efficiency.
• Quantization-aware training (QAT) and post-training quantization (PTQ) were explored to improve model efficiency without severe accuracy degradation, addressing the challenges of bitwidth-accuracy trade-offs in hardware-aware AI.
• A key achievement of this collaboration was demonstrating NAS-driven architectures capable of achieving higher accuracy and lower computational overhead compared to manually designed architectures.
• Two research papers have been submitted to LPS 2025 and EDHPC 2025, detailing these advancements.

Development tools

• Neural Architecture Search (NAS): Applied to automatically design efficient neural network architectures optimized for hardware constraints.
• Optimization Algorithms: Used reinforcement learning and evolutionary search methods (e.g., genetic algorithms) to refine model architectures.
• Model Compression Techniques: Applied post-training quantization (PTQ), quantization-aware training (QAT), pruning, and tensor decomposition to optimize memory and computational requirements.
• Hardware-aware Performance Benchmarking: Integrated real-time latency, memory, and power profiling to ensure models are optimized for onboard deployment.
• Deep Learning Frameworks: Implemented using PyTorch and TensorFlow, leveraging specialized libraries such as TVM, ONNX, and TensorRT for inference acceleration.
• Deployment on Edge AI Devices: Conducted extensive validation on resource-constrained hardware, including NVIDIA Orin, Myriad 2, and other DPU-based architectures, ensuring real-world applicability.

Development Outputs

• The codebase and datasets are proprietary to the company and cannot be publicly shared.
• However, the research findings have led to two submitted papers to the LPS 2025 and EDHPC 2025 conferences, which will detail the methodology, results, and future directions.

Project Description

Introduction

The rise of AI-driven Earth Observation (EO) satellites has introduced new challenges in deploying deep learning models on resource-constrained hardware. Traditional neural network optimization methods rely on post-training compression techniques such as quantization, pruning, and knowledge distillation, which often result in significant accuracy degradation. To address this, Neural Architecture Search (NAS) was explored as a solution to co-design neural networks with hardware constraints in mind from the outset.

This project, conducted in collaboration with ESA Φ-lab, aimed to develop a hardware-aware NAS framework capable of automating model design for edge deployment, ensuring real-time processing capabilities while preserving model accuracy. The framework was validated on burned area segmentation and cloud detection tasks, demonstrating its effectiveness for onboard satellite AI applications.

Methodology

The NAS framework consists of three key components:

1. Search Space (Model Generator): Defines candidate architectures using a structured hierarchy of convolutional and attention-based layers. The model generator incorporates constraints on parameter count, FLOPs, and memory footprint to ensure deployability.
2. Optimizer: Utilizes genetic algorithms and reinforcement learning to iteratively refine architectures, balancing the trade-offs between accuracy and computational efficiency.
3. Hardware-Awareness Block (HAB): Introduces real-time hardware profiling to evaluate and enforce constraints related to memory, inference speed, and power consumption. Unlike conventional NAS approaches, HAB ensures that selected architectures meet real-world edge AI requirements.

This hardware-aware NAS strategy is a fundamental departure from manually tuned architectures, as it dynamically evolves models that are optimized for specific satellite hardware.

Experiments and Results

The NAS framework was evaluated on a burned area segmentation task using Sentinel-2 imagery, which included datasets spanning multiple continents and diverse environmental conditions. The results demonstrated:

• Model size reduction: NAS-generated models were 5.35MB compared to the 355MB baseline (a 93% reduction in memory footprint).
• Accuracy improvement: Despite compression, the NAS-optimized model achieved an IoU of 0.870, outperforming the baseline U-Net's 0.794 IoU.
• Real-time inference capabilities: The optimized models met the latency and power constraints of onboard edge AI processors, ensuring feasibility for real-world deployment.

This study

validated the effectiveness of NAS

for optimizing neural networks for onboard satellite processing, ensuring a balance between

model accuracy, inference speed, and computational complexity

.